  module ip_2port_ram(
      input               sys_clk        ,  //系统时钟
      input               sys_rst_n         //系统复位，低电平有效
      );
  
  //wire define
  wire             clk_50m  ;
  wire             clk_25m  ;

 wire             rst_n   ;
    
 wire             ram_wr_en  ; //ram写使能
 wire    [4:0]    ram_wr_addr; //ram写地址
 wire    [7:0]    ram_wr_data; //ram写数据
 wire             ram_rd_en  ; //ram读使能
 wire    [4:0]    ram_rd_addr; //ram读地址
 wire    [7:0]    ram_rd_data; //ram读数据 
    
 //*****************************************************
 //**                    main code
 //*****************************************************
 
 assign rst_n = sys_rst_n ;
 
 //锁相环模块
 pll_clk u_pll_clk(
     
     .inclk0   (sys_clk),
     .c0       (clk_50m),
     .c1       (clk_25m)

     );
 
 //RAM写模块
 ram_wr u_ram_wr(
     .clk           (clk_50m),
     .rst_n         (rst_n),
       
     .ram_wr_en     (ram_wr_en  ),
     .ram_wr_addr   (ram_wr_addr),
     .ram_wr_data   (ram_wr_data)
     );
 

ram_2port	ram_2port_inst (
	.clock ( clk_50m ),
	.data ( ram_wr_data ),
	.rdaddress ( ram_rd_addr ),
	.rden ( ram_rd_en ),
	.wraddress ( ram_wr_addr ),
	.wren ( ram_wr_en ),
	.q ( ram_rd_data )
	);

 //RAM读模块    
 ram_rd u_ram_rd(
     .clk           (clk_50m),
     .rst_n         (rst_n),
                  
     .ram_rd_en     (ram_rd_en  ),
     .ram_rd_addr   (ram_rd_addr),
     .ram_rd_data   (ram_rd_data)
     );    
 
 endmodule
